Hello Matty C,
We have built it all using ISE, not Vivado, because when we last checked, Vivado had some big problems with inferring the large BRAM units in the design.
That said, if you are willing to try to get it working in Vivado, that would be great. There is some Xilinx documentation somewhere that explains how to import a project from ISE into Vivado.
Also, if you are willing, using either ISE or Vivado, to get it synthesising for the PSRAM version of the board again, that would be great. If you go back in the history of the source code to the start of December 2014, you will find the last PSRAM version of the code. It should just be a case of switching the memory controllers out, updating the UCF file, and resynthesising. However, when I have tried that in the last few months I kept getting some bizarre error message about there not being enough pins, so clearly I was messing something up somewhere. Note that you can't just copy the old CPU and machine container over from the PSRAM version, as there have been quite a few little changes to it since then.
What would be best of all, would be to have some sort of conditional compilation to easily choose between which board you want to synthesise for. Thoughts on that would be most welcome.
And of course any videos and guides would be GREAT!