MEGA65 FORUM

Problems + workarounds with the current (2019-04-23) mega65-core

append delete Terlisimo

Hi,

I have tried building the mega65-core today (2019-04-23) and I've ran into some problems while running "make" in mega65-core "develpment" branch, commit 29b952e.

TL;DR I had to fix some build errors manually, mostly files not being in expected paths. I had to comment out the uart monitor support as I didn't know how to fix it, but finally got the bitstream file built and working. As a result, I can't use monitor_load, but can still program the board with fpgajtag.

My target is nexys4ddr.

Here are the problems I ran into:

1st failure:

--------------

Makefile:419: =============================================================
Makefile:419: ~~~~~~~~~~~~~~~~> Making: src/utilities/vfpgatest.prg
Ophis/bin/ophis -4 src/utilities/vfpgatest.a65 -l src/utilities/vfpgatest.list -m src/utilities/vfpgatest.map -o src/utilities/vfpgatest.prg
src/utilities/vfpgatest.a65:417: Could not read ../../assets/vfpga-bitstream.bin
1 error
make: *** [src/utilities/vfpgatest.prg] Error 1

--------------

Indeed, I don't have that file in mega65-core/assets directory. These are the contents of that directory:

8x8font.png
alphatest.bin
ascii00-7f.png
matrix_banner.txt
matrix.png
mega65_320x64.png
synthesised-60ns.dat
track2-40ns.dat

I've copied alphatest.bin to vfpga-bitstream.bin as it was the only file with the same extension. Not sure if that makes any sense in the long run, but it allowed the build to proceed.

2nd failure:

--------------

( cd src/verilog ; ../../iverilog/driver/iverilog -tvhdl -o ../../src/vhdl/uart_monitor.vhdl.tmp monitor_*.v asym_ram_sdp.v 6502_*.v UART_TX_CTRL.v uart_rx.v )
sh: /home/user/mega65-core/iverilog/lib/ivl/ivlpp: No such file or directory
sh: /home/user/mega65-core/iverilog/lib/ivl/ivl: No such file or directory
make: *** [src/vhdl/uart_monitor.vhdl.tmp] Error 127

--------------

There is no "lib" directory in mega65-core/iverilog. I see there are ivl and ivlpp binaries with paths mega65-core/iverilog/ivl and mega65-core/iverilog/ivlpp/ivlpp

So I manually symlinked the files to existing ones:

mkdir -p /home/user/mega65-core/iverilog/lib/ivl
ln -s /home/user/mega65-core/iverilog/ivlpp/ivlpp /home/user/mega65-core/iverilog/lib/ivl/ivlpp
ln -s /home/user/mega65-core/iverilog/ivl /home/user/mega65-core/iverilog/lib/ivl/ivl

Next error:

--------------

[user@localhost mega65-core]$ make
( cd src/verilog ; ../../iverilog/driver/iverilog -tvhdl -o ../../src/vhdl/uart_monitor.vhdl.tmp monitor_*.v asym_ram_sdp.v 6502_*.v UART_TX_CTRL.v uart_rx.v )
ERROR: Unable to read config file: /home/user/mega65-core/iverilog/lib/ivl/vhdl.conf

--------------

Again, seems to be looking for the vhdl.conf file in the wrong directory. Fixed with

ln -s /home/user/mega65-core/iverilog/tgt-vhdl/vhdl.conf /home/user/mega65-core/iverilog/lib/ivl/vhdl.conf

I think the build process expects iverilog to be manually installed in (with configure/make/make install), and doesn't work as expected when it's just compiled in the submodule dir. Manually symlinking stuff seems to work.

Then I got stuck at:

--------------

( cd src/verilog ; ../../iverilog/driver/iverilog -tvhdl -o ../../src/vhdl/uart_monitor.vhdl.tmp monitor_*.v asym_ram_sdp.v 6502_*.v UART_TX_CTRL.v uart_rx.v )
monitor_top.v:176: error: Unknown module type: monitormem
2 error(s) during elaboration.
*** These modules were missing:
monitormem referenced 1 times.
***
make: *** [src/vhdl/uart_monitor.vhdl.tmp] Error 2

--------------

And here I ran out of ideas. I don't know what the monitormem module type is and what should provide support for it. The only files where it is referenced at all are that monitor_top.v and the main Makefile. Maybe I need a different version of iverilog? I don't see a mention of monitormem there even in the master branch.

Not knowing what to do, I just commented out that monitormem line in monitor_top.v:176

After that I got more complaints about non-existing files, fixed with

ln -s /home/user/mega65-core/iverilog/tgt-vhdl/vhdl.conf /home/user/mega65-core/iverilog/lib/ivl/vhdl.conf
ln -s /home/user/mega65-core/iverilog/tgt-vhdl/vhdl.tgt /home/user/mega65-core/iverilog/lib/ivl/vhdl.tgt

Next, ran into this:

--------------

make[1]: Entering directory `/home/user/mega65-core/src/mega65-fdisk'
cc -o asciih asciih.c
asciih.c: In function ‘main’:
asciih.c:6:3: error: ‘for’ loop initial declarations are only allowed in C99 mode

--------------

I guess it's because I'm running this on Centos 7.6 which comes with gcc4.

Added -std=c99 to mega65-core/src/mega65-fdisk/Makefile:45

With that the build process continued and finally started building stuff with Vivado.

Next, I got some errors like nexys4.vhdl not having declared miso_2 input, but all I really needed was the nexys4ddr target so from then on I went with

make bin/nexys4ddr.mcs

and finally it built!

uploaded it to nexys4 with fpgajtag and it worked.

Would be nice to have the monitor working though since I'm more interested in software development. I'm only a beginner at hardware programming and contributing to the hardware design is beyond my ability at this point.

regards,
Terlisimo

Reply RSS

Replies

append delete #1. gardners

Hello,

Well done on persisting with this!

Please send git pull requests for the changes you made, if you like.

Meanwhile, I added the missing vfpga-bitstream.bit

Yes, the icarus verilog thing is a bit of a horror.
Send me the exact list of commands in a list, and I will add them to the repo.

Paul.

append delete #2. Terlisimo

Hey, thanks for taking the time to look into this!

I've created a pull request on github.

I made another one small fix for Ophis, builds failed on my system where python3 is default.

Could you look into the monitor thing? It seems like monitor_mem.v is missing from the mega65-core/src/verilog directory.
monitor_top.v is referencing it.

append delete #3. Terlisimo

I see that Michael Martin actually converted Ophis to python 3, maybe it will make sense to pull in his changes. I'll go and see about that.

append delete #4. gardners

Well, really we should just try to move away from Ophis to ca65 or another more supported assembler.

monitor_mem.v should get built by some other step in the Makefile. Yes, here is the rule:

$(VERILOGSRCDIR)/monitor_mem.v: $(TOOLDIR)/mempacker/mempacker_v $(BINDIR)/monitor.m65
$(TOOLDIR)/mempacker/mempacker_v -n monitormem -w 12 -s 4096 -f $(VERILOGSRCDIR)/monitor_mem.v $(BINDIR)/monitor.m65@0000

Try making the file explicitly, and tell me if you get an error.

I'll take a look at the pull request -- thanks for that.

Paul.

append delete #5. Terlisimo

Great, thanks!

I'm keen on getting involved with the development. I set out to learn FPGA programming in order to build my own computer from scratch, but the end goal was something like you guys are already doing so I thought I might as well apply my effort here.

I suppose you have some tasks that are nice to have but not priority, like moving to ca65. I'll give that a shot, unless you have a better idea on what I should get started with.

BTW, is this the right place to discuss these kinds of things or is some other place preferred? Google group maybe?

append delete #6. Terlisimo

All right!

monitor_mem.v builds, looks like it's just not listed as a dependency in the main build process.

I'll send a new pull request once I figure out how to fix this

append delete #7. gardners

No worries, and thanks for the pull requests and comments on the commits on github. This is exactly the kind of input that helps us to make the MEGA65 more available to the community.

Paul.

Reply

(Leave this as-is, it’s a trap!)

There is no need to “register”, just enter the same name + password of your choice every time.

Pro tip: Use markup to add links, quotes and more.

Your friendly neighbourhood moderators: Deft, gardners, Ralph Egas