FPGA support for the open source IceStorm toolchain?

append delete sausage

Hi Guys, I'm new. Currently involved with contributions to the Mega65 User Manual.

At the same time I have been toying with FPGA and learning VHDL using the GoBoard. I like it because it is using a Lattice Ice40 FPGA and is therefore compatible with the IceStorm toolchain.

I am considering a Blackice II board because it uses the same IceStorm tooling.

Is there a chance that the project will eventually move from Nexus4 boards to something more open?

Or is it moot point? Could I rather take the Mega65 VHDL files and create a constraint file for my board of choice and be able to build Mega65 hardware using a Blackice II or similar board myself?


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append delete #1. gardners


You could try -- there isn't much xilinx specific that we have done. The design is however currently VERY big, so you might not be able to fit into the lattice part. Give it a go and see how you go, if you want.


append delete #2. LGB

That FPGA seems to have 80Kb block-ram according to the site (if I remember correctly), so it's faaaar too less for this, not even mentioning other FPGA resources and capabilities now. Though I am not even near to Paul's knowledge here, but I think, to port the project to another FPGA (including another vendor) first needs an FPGA which has similar capabilities at least, at the minimum. If I planned something like this, I started with comparing the features/capabilities first to know if it's possible at all in theory.

append delete #3. gardners

In the least you would need a large external SRAM or similar to have any hope, if the part has only 80KB of BRAM built in.


append delete #4. LGB

That's interesting, would it work with the same timing to use an external SRAM if built-in BRAM is not enough anymore? Yeah, SRAM (so no DDR madness, etc), but still, Mega65 has quite tight timing there, at least this is what I thought on this topic.

append delete #5. gardners

I didn't say that that is ALL you would need ;) It would be the starting point.
That said, what we really need to do with the M65 is to pipeline the video memory fetches, so that they can happen quite asynchronously to the bus. That, plus some similar work on the CPU would let us totally decouple the design from the memory latency, provided the overall bandwidth still ended up being high enough in practice. The half-finished new CPU design (which may or may not ever get used) is built based around this concept.

append delete #6. sausage

Thanks for that guys. Ok yes I guess I'm comparing one chip with 80kb to another with 2,700kb, and the available gate numbers don't compare.

The open source toolchain is more geared toward the lattice at the moment. There is an active effort in place to reverse the xilinx 7-series bit stream here:

I'll have to wait for now and stick with LGB's xemu emulator (which is great work BTW).


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