I guess the answer to all the problems you had is just using 50MHz mode, the right CIA timer with IRQ or raster IRQ generation and counters in an IRQ handler, using LDA data (which can be in 32bit address space) and STA to IO register. That would be stable, not have a lot of overhead and be quite straight-forward.
You might end up with strange sample rates and munging your own data but that's not unusual for the poor C64 and family. The actual CPU utilisation on the M65 with this technique would be next to nothing. I think that's important to remember.
A FIFO buffer on the DAC would likely be very small, anyhow... And it would require complication in the implementation in order to use a programmed sample rate and its associated timers.
I can see the argument against using a FIFO and DMAgic for this task. It would just be "nice", that's all. Hmm... I'm not even sure about it. I think I'd prefer to use the DMAgic for other things, so long as the INT feature was implemented.
The thing I'm "most concerned with" is that the DAC is 8bit... Yuck. Lots of noise. I'm assuming its signed... I'd be voting for 16bit DAC over having a FIFO buffer, that's for sure. Even the SIDs have accumulators for waveform generation at 24/21bits and 16bit could still be problematic for mixing any more than four channels.
Yes, 8bit DACs won't do. Forget the FIFO and DMAgic for sampled audio. We need 16 or even 24bit DACs, instead. I must make the request. Hopefully, its possible.